/* sbcm8260Siu.h - Motorola System Interface Unit header file */

/* Copyright 1984-1999 Wind River Systems, Inc. */

/*
modification history
--------------------
01a,06mar99,elk	 created from ppc860Siu.h (ver 01d).
*/

/*
This file contains constants of the System Interface Unit (SIU) for the
Motorola MPC8260 PowerQUICC II microcontroller
*/

#ifndef __INCsbcm8260Siuh
#define __INCsbcm8260Siuh

#ifdef __cplusplus
extern "C" {
#endif

#ifdef	_ASMLANGUAGE
#define CAST(x)
#else /* _ASMLANGUAGE */
typedef volatile UCHAR VCHAR;    /* shorthand for volatile UCHAR */
typedef volatile INT32 VINT32;   /* volatile unsigned word */
typedef volatile INT16 VINT16;   /* volatile unsigned halfword */
typedef volatile INT8 VINT8;     /* volatile unsigned byte */
typedef volatile UINT32 VUINT32; /* volatile unsigned word */
typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
typedef volatile UINT8 VUINT8;   /* volatile unsigned byte */
#define CAST(x) (x)
#endif	/* _ASMLANGUAGE */


/* 
 * MPC8260 internal register/memory map.
 * note that these are offsets from the value stored in the IMMR 
 * register, which is in the PowerPC special register address space
 * at register number 638
 */

/* General SIU registers */

#define SIUMCR(base)    (CAST(VUINT32 *)(base + 0x10000)) /* SIU Module Config*/
#define SYPCR(base)     (CAST(VUINT32 *)(base + 0x10004)) /* Protection Ctrl */
#define SWT(base)       (CAST(VUINT32 *)(base + 0x10008)) /* SW watch dog */
#define SWSR(base)      (CAST(VUINT16 *)(base + 0x1000E)) /* SW Service Reg */
/* 10010-10023 RESERVED */
#define BCR(base)       (CAST(VUINT32 *)(base + 0x10024)) /* BUS Config Reg */
#define PPC_ACR(base)   (CAST(VUINT8  *)(base + 0x10028)) /* 60x bus arb conf */
#define PPC_ALRH(base)  (CAST(VUINT32 *)(base + 0x1002C)) /* 60x bus arb lvl */
#define PPC_ALRL(base)  (CAST(VUINT32 *)(base + 0x10030)) /* 60x bus arb lvl */
#define LCL_ACR(base)   (CAST(VUINT8  *)(base + 0x10034)) /* Lcl bus arb conf */
#define LCL_ALRH(base)  (CAST(VUINT32 *)(base + 0x10038)) /* Lcl bus arb lvl */
#define LCL_ALRL(base)  (CAST(VUINT32 *)(base + 0x1003C)) /* Lcl bus arb lvl */
#define TESCR1(base)    (CAST(VUINT32 *)(base + 0x10040)) /* 60x xfer err 1 */
#define TESCR2(base)    (CAST(VUINT32 *)(base + 0x10044)) /* 60x xfer err 2 */
#define L_TESCR1(base)  (CAST(VUINT32 *)(base + 0x10048)) /* Lcl xfer err 1 */
#define L_TESCR2(base)  (CAST(VUINT32 *)(base + 0x1004C)) /* Lcl xfer err 2 */
#define PDTEA(base)     (CAST(VUINT32 *)(base + 0x10050)) /* 60x DMA xfer err */
#define PDTEM(base)     (CAST(VUINT8  *)(base + 0x10054)) /* 60x DMA xfer err */
/* 10055 RESERVED (24 Bits)*/
#define LDTEA(base)     (CAST(VUINT32 *)(base + 0x10058)) /* Lcl DMA xfer err */
#define LDTEM(base)     (CAST(VUINT8  *)(base + 0x1005C)) /* Lcl DMA xfer err */
/* 1005D-100FF RESERVED (163 bytes) */

/* MEMC (Memory Controller) registers */

#define BR0(base)       (CAST(VUINT32 *)(base + 0x10100)) /* Base Reg bank 0 */
#define OR0(base)       (CAST(VUINT32 *)(base + 0x10104)) /* Option Reg bank 0*/
#define BR1(base)       (CAST(VUINT32 *)(base + 0x10108)) /* Base Reg bank 1 */
#define OR1(base)       (CAST(VUINT32 *)(base + 0x1010C)) /* Option Reg bank 1*/
#define BR2(base)       (CAST(VUINT32 *)(base + 0x10110)) /* Base Reg bank 2 */
#define OR2(base)       (CAST(VUINT32 *)(base + 0x10114)) /* Option Reg bank 2*/
#define BR3(base)       (CAST(VUINT32 *)(base + 0x10118)) /* Base Reg bank 3 */
#define OR3(base)       (CAST(VUINT32 *)(base + 0x1011C)) /* Option Reg bank 3*/
#define BR4(base)       (CAST(VUINT32 *)(base + 0x10120)) /* Base Reg bank 4 */
#define OR4(base)       (CAST(VUINT32 *)(base + 0x10124)) /* Option Reg bank 4*/
#define BR5(base)       (CAST(VUINT32 *)(base + 0x10128)) /* Base Reg bank 5 */
#define OR5(base)       (CAST(VUINT32 *)(base + 0x1012C)) /* Option Reg bank 5*/
#define BR6(base)       (CAST(VUINT32 *)(base + 0x10130)) /* Base Reg bank 6 */
#define OR6(base)       (CAST(VUINT32 *)(base + 0x10134)) /* Option Reg bank 6*/
#define BR7(base)       (CAST(VUINT32 *)(base + 0x10138)) /* Base Reg bank 7 */
#define OR7(base)       (CAST(VUINT32 *)(base + 0x1013C)) /* Option Reg bank 7*/
#define BR8(base)       (CAST(VUINT32 *)(base + 0x10140)) /* Base Reg bank 8 */
#define OR8(base)       (CAST(VUINT32 *)(base + 0x10144)) /* Option Reg bank 8*/
#define BR9(base)       (CAST(VUINT32 *)(base + 0x10148)) /* Base Reg bank 9 */
#define OR9(base)       (CAST(VUINT32 *)(base + 0x1014C)) /* Option Reg bank 9*/
#define BR10(base)      (CAST(VUINT32 *)(base + 0x10150)) /* Base Reg bank 10*/
#define OR10(base)      (CAST(VUINT32 *)(base + 0x10154)) /* Option Reg bnk 10*/
#define BR11(base)      (CAST(VUINT32 *)(base + 0x10158)) /* Base Reg bank 11*/
#define OR11(base)      (CAST(VUINT32 *)(base + 0x1015C)) /* Option Reg bnk 11*/

#define MAR(base)       (CAST(VUINT32 *)(base + 0x10168)) /* Memory Address */
#define MAMR(base)      (CAST(VUINT32 *)(base + 0x10170)) /* Machine A Mode */
#define MBMR(base)      (CAST(VUINT32 *)(base + 0x10174)) /* Machine B Mode */
#define MCMR(base)      (CAST(VUINT32 *)(base + 0x10178)) /* Machine C Mode */
#define MPTPR(base)     (CAST(VUINT16 *)(base + 0x10184)) /* Mem Timer Prescal*/
#define MDR(base)       (CAST(VUINT32 *)(base + 0x10188)) /* Memory Data reg */
#define PSDMR(base)     (CAST(VUINT32 *)(base + 0x10190)) /* 60x SDRAM mode */
#define LSDMR(base)     (CAST(VUINT32 *)(base + 0x10194)) /* Lcl SDRAM mode */
#define PURT(base)      (CAST(VUINT8  *)(base + 0x10198)) /* 60x UPM refrsh */
#define PSRT(base)      (CAST(VUINT8  *)(base + 0x1019C)) /* 60x SDRAM refrsh */
#define LURT(base)      (CAST(VUINT8  *)(base + 0x101A0)) /* Lcl UPM refrsh */
#define LSRT(base)      (CAST(VUINT8  *)(base + 0x101A4)) /* Lcl SDRAM refrsh */
#define IMMR(base)      (CAST(VUINT32 *)(base + 0x101A8)) /* Intern Mem Map Rg*/

/* System Integration Timers */

/* 10200-1021F RESERVED */
#define TMCNTSC(base)   (CAST(VUINT16 *)(base + 0x10220)) /* T.C. Status Ctrl */
#define TMCNT(base)     (CAST(VUINT32 *)(base + 0x10224)) /* Time count */
#define TMCNTAL(base)   (CAST(VUINT32 *)(base + 0x1022C)) /* Time cntr alrm */

#define PISCR(base)     (CAST(VUINT16 *)(base + 0x10240)) /* PIT Status Ctrl */
#define PITC(base)      (CAST(VUINT32 *)(base + 0x10244)) /* PIT Count */
#define PITR(base)      (CAST(VUINT32 *)(base + 0x10248)) /* PIT */

/* Interrupt Controller */

#define SICR(base)      (CAST(VUINT16 *)(base + 0x10C00)) /* SIU intr conf */
#define SIVEC(base)     (CAST(VUINT32 *)(base + 0x10C04)) /* SIU intr vect */
#define SIPNR_H(base)   (CAST(VUINT32 *)(base + 0x10C08)) /* SIU intr pend */
#define SIPNR_L(base)   (CAST(VUINT32 *)(base + 0x10C0C)) /* SIU intr pend */
#define SIPRR(base)     (CAST(VUINT32 *)(base + 0x10C10)) /* SIU intr prior */
#define SCPRR_H(base)   (CAST(VUINT32 *)(base + 0x10C14)) /* CPM intr prior */
#define SCPRR_L(base)   (CAST(VUINT32 *)(base + 0x10C18)) /* CPM intr prior */
#define SIMR_H(base)    (CAST(VUINT32 *)(base + 0x10C1C)) /* SIU intr mask */
#define SIMR_L(base)    (CAST(VUINT32 *)(base + 0x10C20)) /* SIU intr mask */
#define SIEXR(base)     (CAST(VUINT32 *)(base + 0x10C24)) /* SIU ext intr */

/* Clocks and Reset */

#define SCCR(base)      (CAST(VUINT32 *)(base + 0x10C80)) /* System Clock Ctrl*/
#define SCMR(base)      (CAST(VUINT32 *)(base + 0x10C88)) /* System Clock Mode*/
#define RSR(base)       (CAST(VUINT32 *)(base + 0x10C90)) /* Reset Status Reg */
#define RMR(base)       (CAST(VUINT32 *)(base + 0x10C94)) /* Reset Mode reg */

/* Input/Output Port */

#define PDIRA(base)     (CAST(VUINT32 *)(base + 0x10D00)) /* Port A data dir */
#define PPARA(base)     (CAST(VUINT32 *)(base + 0x10D04)) /* Port A pin assign*/
#define PSORA(base)     (CAST(VUINT32 *)(base + 0x10D08)) /* Port A options */
#define PODRA(base)     (CAST(VUINT32 *)(base + 0x10D0C)) /* Port A open drain*/
#define PDATA(base)     (CAST(VUINT32 *)(base + 0x10D10)) /* Port A data reg */
/* 10D14-10D1F RESERVED */
#define PDIRB(base)     (CAST(VUINT32 *)(base + 0x10D20)) /* Port B data dir */
#define PPARB(base)     (CAST(VUINT32 *)(base + 0x10D24)) /* Port B pin assign*/
#define PSORB(base)     (CAST(VUINT32 *)(base + 0x10D28)) /* Port B options */
#define PODRB(base)     (CAST(VUINT32 *)(base + 0x10D2C)) /* Port B open drain*/
#define PDATB(base)     (CAST(VUINT32 *)(base + 0x10D30)) /* Port B data reg */
/* 10D34-10D3F RESERVED */
#define PDIRC(base)     (CAST(VUINT32 *)(base + 0x10D40)) /* Port C data dir */
#define PPARC(base)     (CAST(VUINT32 *)(base + 0x10D44)) /* Port C pin assign*/
#define PSORC(base)     (CAST(VUINT32 *)(base + 0x10D48)) /* Port C options */
#define PODRC(base)     (CAST(VUINT32 *)(base + 0x10D4C)) /* Port C open drain*/
#define PDATC(base)     (CAST(VUINT32 *)(base + 0x10D50)) /* Port C data reg */
/* 10D54-10D5F RESERVED */
#define PDIRD(base)     (CAST(VUINT32 *)(base + 0x10D60)) /* Port D data dir */
#define PPARD(base)     (CAST(VUINT32 *)(base + 0x10D64)) /* Port D pin assign*/
#define PSORD(base)     (CAST(VUINT32 *)(base + 0x10D68)) /* Port D options */
#define PODRD(base)     (CAST(VUINT32 *)(base + 0x10D6C)) /* Port D open drain*/
#define PDATD(base)     (CAST(VUINT32 *)(base + 0x10D70)) /* Port D data reg */

/* CPM Timers */

#define TGCR1(base)     (CAST(VUINT8  *)(base + 0x10D80)) /* Tmr1&2 glob conf */
#define TGCR2(base)     (CAST(VUINT8  *)(base + 0x10D84)) /* Tmr3&4 glob conf */
/* 10D85-10D8F RESERVED */
#define TMR1(base)      (CAST(VUINT16 *)(base + 0x10D90)) /* Timer 1 mode  */
#define TMR2(base)      (CAST(VUINT16 *)(base + 0x10D92)) /* Timer 2 mode  */
#define TRR1(base)      (CAST(VUINT16 *)(base + 0x10D94)) /* Tmr 1 reference */
#define TRR2(base)      (CAST(VUINT16 *)(base + 0x10D96)) /* Tmr 2 reference */
#define TCR1(base)      (CAST(VUINT16 *)(base + 0x10D98)) /* Tmr 1 capture  */
#define TCR2(base)      (CAST(VUINT16 *)(base + 0x10D9A)) /* Tmr 2 capture  */
#define TCN1(base)      (CAST(VUINT16 *)(base + 0x10D9C)) /* Timer 1 counter */
#define TCN2(base)      (CAST(VUINT16 *)(base + 0x10D9E)) /* Timer 2 counter */
#define TMR3(base)      (CAST(VUINT16 *)(base + 0x10DA0)) /* Timer 3 mode  */
#define TMR4(base)      (CAST(VUINT16 *)(base + 0x10DA2)) /* Timer 4 mode  */
#define TRR3(base)      (CAST(VUINT16 *)(base + 0x10DA4)) /* Tmr 3 reference */
#define TRR4(base)      (CAST(VUINT16 *)(base + 0x10DA6)) /* Tmr 4 reference */
#define TCR3(base)      (CAST(VUINT16 *)(base + 0x10DA8)) /* Tmr 3 capture  */
#define TCR4(base)      (CAST(VUINT16 *)(base + 0x10DAA)) /* Tmr 4 capture  */
#define TCN3(base)      (CAST(VUINT16 *)(base + 0x10DAC)) /* Timer 3 counter */
#define TCN4(base)      (CAST(VUINT16 *)(base + 0x10DAE)) /* Timer 4 counter */
#define TER1(base)      (CAST(VUINT16 *)(base + 0x10DB0)) /* Timer 1 event  */
#define TER2(base)      (CAST(VUINT16 *)(base + 0x10DB2)) /* Timer 2 event  */
#define TER3(base)      (CAST(VUINT16 *)(base + 0x10DB4)) /* Timer 3 event  */
#define TER4(base)      (CAST(VUINT16 *)(base + 0x10DB6)) /* Timer 4 event  */
/* 10DB8-11017 RESERVED */

/* SDMA-General */

#define SDSR(base)	(CAST(VUINT8  *)(base + 0x11018)) /* SDMA Status Reg */
#define SDMR(base)	(CAST(VUINT8  *)(base + 0x1101C)) /* SDMA Mask Reg */

/* IDMA */

#define IDSR1(base)	(CAST(VUINT8  *)(base + 0x11020)) /* IDMA 1 Event Reg*/
#define IDMR1(base)	(CAST(VUINT8  *)(base + 0x11024)) /* IDMA 1 Mask Reg */
#define IDSR2(base)	(CAST(VUINT8  *)(base + 0x11028)) /* IDMA 2 Event Reg*/
#define IDMR2(base)	(CAST(VUINT8  *)(base + 0x1102C)) /* IDMA 2 Mask Reg */
#define IDSR3(base)	(CAST(VUINT8  *)(base + 0x11030)) /* IDMA 3 Event Reg*/
#define IDMR3(base)	(CAST(VUINT8  *)(base + 0x11034)) /* IDMA 3 Mask Reg */
#define IDSR4(base)	(CAST(VUINT8  *)(base + 0x11038)) /* IDMA 4 Event Reg*/
#define IDMR4(base)	(CAST(VUINT8  *)(base + 0x1103C)) /* IDMA 4 Mask Reg */
/* 1103D-112FF RESERVED */

/* FCC1 */

#define GFMR1(base)	(CAST(VUINT32 *)(base + 0x11300)) /* FCC1 General Mode*/
#define FPSMR1(base)	(CAST(VUINT32 *)(base + 0x11304)) /* FCC1 Proto-Spec */
#define FTODR1(base)	(CAST(VUINT16 *)(base + 0x11308)) /* FCC1 TOD reg */
/* 1130A RESERVED */
#define FDSR1(base)	(CAST(VUINT16 *)(base + 0x1130C)) /* FCC1 data sync */
/* 1130E RESERVED */
#define FCCE1(base)	(CAST(VUINT32 *)(base + 0x11310)) /* FCC1 Event Reg */
#define FCCM1(base)	(CAST(VUINT32 *)(base + 0x11314)) /* FCC1 Mask Reg */
#define FCCS1(base)	(CAST(VUINT8  *)(base + 0x11318)) /* FCC1 Status Reg */
/* 11319 RESERVED */
#define FTIRR1_PHY0(base) (CAST(VUINT8 *)(base + 0x1131C)) /* FCC1 transmit   */
#define FTIRR1_PHY1(base) (CAST(VUINT8 *)(base + 0x1131D)) /* internal rate   */
#define FTIRR1_PHY2(base) (CAST(VUINT8 *)(base + 0x1131E)) /* registers for   */
#define FTIRR1_PHY3(base) (CAST(VUINT8 *)(base + 0x1131F)) /* PHY0-3          */

/* FCC2 */

#define GFMR2(base)	(CAST(VUINT32 *)(base + 0x11320)) /* FCC2 General Mode*/
#define FPSMR2(base)	(CAST(VUINT32 *)(base + 0x11324)) /* FCC2 Proto-Spec */
#define FTODR2(base)	(CAST(VUINT16 *)(base + 0x11328)) /* FCC2 TOD reg */
/* 1132A RESERVED */
#define FDSR2(base)	(CAST(VUINT16 *)(base + 0x1132C)) /* FCC2 data sync */
/* 1132E RESERVED */
#define FCCE2(base)	(CAST(VUINT32 *)(base + 0x11330)) /* FCC2 Event Reg */
#define FCCM2(base)	(CAST(VUINT32 *)(base + 0x11334)) /* FCC2 Mask Reg */
#define FCCS2(base)	(CAST(VUINT8  *)(base + 0x11338)) /* FCC2 Status Reg */
/* 11339 RESERVED */
#define FTIRR2_PHY0(base) (CAST(VUINT8 *)(base + 0x1133C)) /* FCC2 transmit   */
#define FTIRR2_PHY1(base) (CAST(VUINT8 *)(base + 0x1133D)) /* internal rate   */
#define FTIRR2_PHY2(base) (CAST(VUINT8 *)(base + 0x1133E)) /* registers for   */
#define FTIRR2_PHY3(base) (CAST(VUINT8 *)(base + 0x1133F)) /* PHY0-3          */

/* FCC3 */

#define GFMR3(base)	(CAST(VUINT32 *)(base + 0x11340)) /* FCC3 General Mode*/
#define FPSMR3(base)	(CAST(VUINT32 *)(base + 0x11344)) /* FCC3 Proto-Spec */
#define FTODR3(base)	(CAST(VUINT16 *)(base + 0x11348)) /* FCC3 TOD reg */
/* 1134A RESERVED */
#define FDSR3(base)	(CAST(VUINT16 *)(base + 0x1134C)) /* FCC3 data sync */
/* 1134E RESERVED */
#define FCCE3(base)	(CAST(VUINT32 *)(base + 0x11350)) /* FCC3 Event Reg */
#define FCCM3(base)	(CAST(VUINT32 *)(base + 0x11354)) /* FCC3 Mask Reg */
#define FCCS3(base)	(CAST(VUINT8  *)(base + 0x11358)) /* FCC3 Status Reg */
/* 11359-113FF RESERVED */

/* Baud Rate Generation - BRGs 5-8 */

#define	BRGC5(base)	(CAST(VUINT32 *)(base + 0x115F0)) /* BRG5 Config Reg */
#define	BRGC6(base)	(CAST(VUINT32 *)(base + 0x115F4)) /* BRG6 Config Reg */
#define	BRGC7(base)	(CAST(VUINT32 *)(base + 0x115F8)) /* BRG7 Config Reg */
#define	BRGC8(base)	(CAST(VUINT32 *)(base + 0x115FC)) /* BRG8 Config Reg */
/* 11600-1185F RESERVED */

/* I2C */

#define	I2MOD(base)	(CAST(VUINT8  *)(base + 0x11860)) /* I2C Mode Reg */
#define	I2ADD(base)	(CAST(VUINT8  *)(base + 0x11864)) /* I2C Address Reg */
#define	I2BRG(base)	(CAST(VUINT8  *)(base + 0x11868)) /* I2C BRG Reg */
#define	I2COM(base)	(CAST(VUINT8  *)(base + 0x1186C)) /* I2C Command Reg */
#define	I2CER(base)	(CAST(VUINT8  *)(base + 0x11870)) /* I2C Event Reg */
#define	I2CMR(base)	(CAST(VUINT8  *)(base + 0x11874)) /* I2C Mask Reg */
/* 11875-119BF RESERVED */

/* Communication Processor register set */

#define	CPCR(base)	(CAST(VUINT32 *)(base + 0x119C0)) /* Com Processor Cmd*/
#define	RCCR(base)	(CAST(VUINT32 *)(base + 0x119C4)) /* CP Config Reg */
/* 119C8-119D5 RESERVED */
#define	RTER(base)	(CAST(VUINT16 *)(base + 0x119D6)) /* CP Timers Event*/
#define	RTMR(base)	(CAST(VUINT16 *)(base + 0x119DA)) /* CP Timers Mask */
#define	RTSCR(base)	(CAST(VUINT16 *)(base + 0x119DC)) /* CP Time Stp Ctrl */
/* 119DE RESERVED */
#define	RTSR(base)	(CAST(VUINT32 *)(base + 0x119E0)) /* CP Time Stamp */

/* Baud Rate Generation - BRGs 1-4 */

#define	BRGC1(base)	(CAST(VUINT32 *)(base + 0x119F0)) /* BRG1 Config Reg */
#define	BRGC2(base)	(CAST(VUINT32 *)(base + 0x119F4)) /* BRG2 Config Reg */
#define	BRGC3(base)	(CAST(VUINT32 *)(base + 0x119F8)) /* BRG3 Config Reg */
#define	BRGC4(base)	(CAST(VUINT32 *)(base + 0x119FC)) /* BRG4 Config Reg */

/* SCC 1 register set */

#define GSMR_L1(base)	(CAST(VUINT32 *)(base + 0x11A00)) /* SCC1 General Mode*/
#define GSMR_H1(base)	(CAST(VUINT32 *)(base + 0x11A04)) /* SCC1 General Mode*/
#define PSMR1(base)	(CAST(VUINT16 *)(base + 0x11A08)) /* SCC1 Proto. Spec */
/* 11A0A RESERVED */
#define TODR1(base)	(CAST(VUINT16 *)(base + 0x11A0C)) /* SCC1 Tx On Demand*/
#define DSR1(base)	(CAST(VUINT16 *)(base + 0x11A0E)) /* SCC1 Data Sync */
#define SCCE1(base)	(CAST(VUINT16 *)(base + 0x11A10)) /* SCC1 Event Reg */
#define SCCM1(base)	(CAST(VUINT16 *)(base + 0x11A14)) /* SCC1 Mask Reg */
#define SCCS1(base)	(CAST(VUINT8  *)(base + 0x11A17)) /* SCC1 Status Reg */
/* 11A18-11A1F RESERVED */

/* SCC 2 register set */

#define GSMR_L2(base)	(CAST(VUINT32 *)(base + 0x11A20)) /* SCC2 General Mode*/
#define GSMR_H2(base)	(CAST(VUINT32 *)(base + 0x11A24)) /* SCC2 General Mode*/
#define PSMR2(base)	(CAST(VUINT16 *)(base + 0x11A28)) /* SCC2 Proto. Spec */
/* 11A2A RESERVED */
#define TODR2(base)	(CAST(VUINT16 *)(base + 0x11A2C)) /* SCC2 Tx On Demand*/
#define DSR2(base)	(CAST(VUINT16 *)(base + 0x11A2E)) /* SCC2 Data Sync */
#define SCCE2(base)	(CAST(VUINT16 *)(base + 0x11A30)) /* SCC2 Event Reg */
#define SCCM2(base)	(CAST(VUINT16 *)(base + 0x11A34)) /* SCC2 Mask Reg */
#define SCCS2(base)	(CAST(VUINT8  *)(base + 0x11A37)) /* SCC2 Status Reg */
/* 11A38-11A3F RESERVED */

/* SCC 3 register set */

#define GSMR_L3(base)	(CAST(VUINT32 *)(base + 0x11A40)) /* SCC3 General Mode*/
#define GSMR_H3(base)	(CAST(VUINT32 *)(base + 0x11A44)) /* SCC3 General Mode*/
#define PSMR3(base)	(CAST(VUINT16 *)(base + 0x11A48)) /* SCC3 Proto. Spec */
/* 11A4A RESERVED */
#define TODR3(base)	(CAST(VUINT16 *)(base + 0x11A4C)) /* SCC3 Tx On Demand*/
#define DSR3(base)	(CAST(VUINT16 *)(base + 0x11A4E)) /* SCC3 Data Sync */
#define SCCE3(base)	(CAST(VUINT16 *)(base + 0x11A50)) /* SCC3 Event Reg */
#define SCCM3(base)	(CAST(VUINT16 *)(base + 0x11A54)) /* SCC3 Mask Reg */
#define SCCS3(base)	(CAST(VUINT8  *)(base + 0x11A57)) /* SCC3 Status Reg */
/* 11A58-11A5F RESERVED */

/* SCC 4 register set */

#define GSMR_L4(base)	(CAST(VUINT32 *)(base + 0x11A60)) /* SCC4 General Mode*/
#define GSMR_H4(base)	(CAST(VUINT32 *)(base + 0x11A64)) /* SCC4 General Mode*/
#define PSMR4(base)	(CAST(VUINT16 *)(base + 0x11A68)) /* SCC4 Proto. Spec */
/* 11A6A RESERVED */
#define TODR4(base)	(CAST(VUINT16 *)(base + 0x11A6C)) /* SCC4 Tx On Demand*/
#define DSR4(base)	(CAST(VUINT16 *)(base + 0x11A6E)) /* SCC4 Data Sync */
#define SCCE4(base)	(CAST(VUINT16 *)(base + 0x11A70)) /* SCC4 Event Reg */
#define SCCM4(base)	(CAST(VUINT16 *)(base + 0x11A74)) /* SCC2 Mask Reg */
#define SCCS4(base)	(CAST(VUINT8  *)(base + 0x11A77)) /* SCC4 Status Reg */
/* 11A78-11A7F RESERVED */

/* SMC 1 register set */

#define	SMCMR1(base)	(CAST(VUINT16 *)(base + 0x11A82)) /* SMC1 Mode Reg */
#define	SMCE1(base)	(CAST(VUINT8  *)(base + 0x11A86)) /* SMC1 Event Reg */
#define	SMCM1(base)	(CAST(VUINT8  *)(base + 0x11A8A)) /* SMC1 Mask Reg */
/* 11A8B-11A91 RESERVED */

/* SMC 2 register set */

#define	SMCMR2(base)	(CAST(VUINT16 *)(base + 0x11A92)) /* SMC2 Mode Reg */
#define	SMCE2(base)	(CAST(VUINT8  *)(base + 0x11A96)) /* SMC2 Event Reg */
#define	SMCM2(base)	(CAST(VUINT8  *)(base + 0x11A9A)) /* SMC2 Mask Reg */
/* 11A9B-11A9F RESERVED */

/* SPI register set */

#define	SPMODE(base)	(CAST(VUINT16 *)(base + 0x11AA0)) /* SPI Mode Reg */
/* 11AA2 RESERVED */
#define	SPIE(base)	(CAST(VUINT8  *)(base + 0x11AA6)) /* SPI Event Reg */
/* 11AA7 RESERVED */
#define	SPIM(base)	(CAST(VUINT8  *)(base + 0x11AAA)) /* SPI Mask Reg */
/* 11AAB RESERVED */
#define	SPCOM(base)	(CAST(VUINT8  *)(base + 0x11AAD)) /* SPI Command Reg */
/* 11AAE-11AFF RESERVED */

/* CPM Mux */

#define	CMXSI1CR(base)	(CAST(VUINT8  *)(base + 0x11B00)) /* mux SI1 clk rte */
#define	CMXSI2CR(base)	(CAST(VUINT8  *)(base + 0x11B02)) /* mux SI2 clk rte */
/* 11B03 RESERVED */
#define	CMXFCR(base)	(CAST(VUINT32 *)(base + 0x11B04)) /* mux FCC clk rte */
#define	CMXSCR(base)	(CAST(VUINT32 *)(base + 0x11B08)) /* mux SCC clk rte */
#define	CMXSMR(base)	(CAST(VUINT8  *)(base + 0x11B0C)) /* mux SMC clk rte */
/* 11B0D RESERVED */
#define	CMXUAR(base)	(CAST(VUINT16 *)(base + 0x11B0E)) /* mux UTOPIA adr */
/* 11B10-11B1F RESERVED */

/* SI1 Registers */

#define	SI1AMR(base)	(CAST(VUINT16 *)(base + 0x11B20)) /* SI1 TDMA1 mode */
#define	SI1BMR(base)	(CAST(VUINT16 *)(base + 0x11B22)) /* SI1 TDMB1 mode */
#define	SI1CMR(base)	(CAST(VUINT16 *)(base + 0x11B24)) /* SI1 TDMC1 mode */
#define	SI1DMR(base)	(CAST(VUINT16 *)(base + 0x11B26)) /* SI1 TDMD1 mode */
#define	SI1GMR(base)	(CAST(VUINT8  *)(base + 0x11B28)) /* SI1 global mode */
#define	SI1CMDR(base)	(CAST(VUINT8  *)(base + 0x11B2A)) /* SI1 command */
#define	SI1STR(base)	(CAST(VUINT8  *)(base + 0x11B2C)) /* SI1 status */
#define	SI1RSR(base)	(CAST(VUINT16 *)(base + 0x11B2E)) /* SI1 RAM shadow */

/* MCC1 Registers */

#define	MCCE1(base)	(CAST(VUINT16 *)(base + 0x11B30)) /* MCC1 event */
#define	MCCM1(base)	(CAST(VUINT16 *)(base + 0x11B34)) /* MCC1 mask */
/* 11B36 RESERVED */
#define	MCCF1(base)	(CAST(VUINT8  *)(base + 0x11B38)) /* MCC1 conf */
/* 11B39-11B3F */

/* SI2 Registers */

#define	SI2AMR(base)	(CAST(VUINT16 *)(base + 0x11B40)) /* SI2 TDMA2 mode */
#define	SI2BMR(base)	(CAST(VUINT16 *)(base + 0x11B42)) /* SI2 TDMB2 mode */
#define	SI2CMR(base)	(CAST(VUINT16 *)(base + 0x11B44)) /* SI2 TDMC2 mode */
#define	SI2DMR(base)	(CAST(VUINT16 *)(base + 0x11B46)) /* SI2 TDMD2 mode */
#define	SI2GMR(base)	(CAST(VUINT8  *)(base + 0x11B48)) /* SI2 global mode */
/* 11B49 RESERVED */
#define	SI2CMDR(base)	(CAST(VUINT8  *)(base + 0x11B4A)) /* SI2 command */
/* 11B49 RESERVED */
#define	SI2STR(base)	(CAST(VUINT8  *)(base + 0x11B4C)) /* SI2 status */
/* 11B4D RESERVED */
#define	SI2RSR(base)	(CAST(VUINT16 *)(base + 0x11B4E)) /* SI2 RAM shadow */

/* MCC2 Registers */

#define	MCCE2(base)	(CAST(VUINT16 *)(base + 0x11B50)) /* MCC2 event */
#define	MCCM2(base)	(CAST(VUINT16 *)(base + 0x11B54)) /* MCC2 mask */
#define	MCCF2(base)	(CAST(VUINT8  *)(base + 0x11B58)) /* MCC2 conf */
/* 11B59-11FFF */

/* SIU Module Configuration register bit definition (SIUMCR - 0x10000) */

#define SIUMCR_BBD              0x80000000      /* Bus busy disable */
#define SIUMCR_ESE              0x40000000      /* External snoop enable */
#define SIUMCR_PBSE             0x20000000      /* Parity byte select enable */
#define SIUMCR_CDSI             0x10000000      /* Core disable */
#define SIUMCR_DPPC             0x0c000000      /* Data parity pins Config. */
#define SIUMCR_L2CPC            0x03000000      /* L2 cache pins Config. */
#define SIUMCR_LBPC             0x00c00000      /* Local bus pins Config. */
#define SIUMCR_APPC             0x00300000      /* Address parity pins Config */
#define SIUMCR_CS10PC           0x000c0000      /* Chip select 10-pin Config. */
#define SIUMCR_BCTLC            0x00030000      /* Buffer control Config. */
#define SIUMCR_MMR              0x0000c000      /* Mask masters requests */
#define SIUMCR_LPBSE            0x00004000      /* Local bus parity select ena*/

/* System Portection Control register bit definition (SYPCR - 0x10004) */

#define SYPCR_SWTC	0xffff0000	/* Software Watchdog Timer Count */
#define SYPCR_BMT	0x0000ff00	/* Bus Monitor Timing */
#define SYPCR_PBME	0x00000080	/* 60x Bus Monitor Enable */
#define SYPCR_LBME	0x00000040	/* Local Bus Monitor Enable */
#define SYPCR_SWE	0x00000004	/* Software Watchdog Enable */
#define SYPCR_SWRI	0x00000002	/* Software Watchdog Reset/Int Select */
#define SYPCR_SWP	0x00000001	/* Software Watchdog Prescale */


/* Memory Periodic Timer Prescaler Register bit definition (MPTPR - 0x10184) */

#define MPTPR_PTP_MSK	0xff00		/* Periodic Timers Prescaler Mask */
#define MPTPR_PTP_DIV2	0x2000		/* BRGCLK divided by 2 */
#define MPTPR_PTP_DIV4	0x1000		/* BRGCLK divided by 4 */
#define MPTPR_PTP_DIV8	0x0800		/* BRGCLK divided by 8 */
#define MPTPR_PTP_DIV16	0x0400		/* BRGCLK divided by 16 */
#define MPTPR_PTP_DIV32	0x0200		/* BRGCLK divided by 32 */
#define MPTPR_PTP_DIV64	0x0100		/* BRGCLK divided by 64 */


/* Base Register bit definition (BRx - 0xXXXXX) */

#define BR_BA_MSK	0xffff8000	/* Base Address Mask */
#define BR_PS_MSK	0x00001800	/* Port Size Mask */
#define BR_DECC_MSK     0x00000600	/* Data Error Correction and Checking*/
#define BR_WP		0x00000100	/* Write Protect */
#define BR_MS_MSK	0x000000e0	/* Machine Select Mask */
#define BR_MS_GPCM_60x  0x00000000	/* G.P.C.M. Machine Select - 60x bus */
#define BR_MS_GPCM_LCL  0x00000020	/* G.P.C.M. Machine Select - Local */
#define BR_MS_SDRAM_60x 0x00000040	/* SDRAM Machine Select - 60x bus */
#define BR_MS_SDRAM_LCL 0x00000080	/* SDRAM Machine Select - Local */
#define BR_MS_UPMA	0x000000a0	/* U.P.M.A Machine Select */
#define BR_MS_UPMB	0x000000c0	/* U.P.M.B Machine Select */
#define BR_MS_UPMC	0x000000e0	/* U.P.M.C Machine Select */
#define BR_EMEMC        0x00000010	/* External MEMC Enable */
#define BR_ATOM_MSK     0x0000000c	/* Atomic Operation */
#define BR_DR           0x00000002	/* Data Pipelining */
#define BR_V		0x00000001	/* Bank Valid */


#ifdef INCLUDE_SDRAM_MODE
/* Option Register bit definition (ORx - 0xXXXXX) */

#define OR_SDAM_MSK     0xfff00000	/* SDRAM Address Mask */
#define OR_LSDAM_MSK    0x000f8000	/* Lower SDRAM Address Mask */
#define OR_BPD_MSK      0x00006000	/* Banks per Device */
#define OR_ROWST_MSK    0x00001c00	/* Row Start Address Bit */
#define OR_NUMR_MSK     0x000001c0	/* Number of Row Address Lines */
#define OR_PMSEL        0x00000020	/* Page Mode Select */
#define OR_IBID         0x00000010	/* Internal Bank Interleaving */
#endif

/* Machine A Mode Register bit definition (MAMR - 0x10170) */

#define MAMR_BSEL       0x80000000      /* Bus select */
#define MAMR_RFEN       0x40000000      /* Refresh enable */
#define MAMR_OP_MSK     0x30000000      /* Command opcode mask */
#define MAMR_AMA_MSK    0x07000000      /* Addess Multiplexing size A */
#define MAMR_AMA_TYPE_0 0x00000000      /* Addess Multiplexing Type 0 */
#define MAMR_AMA_TYPE_1 0x01000000      /* Addess Multiplexing Type 1 */
#define MAMR_AMA_TYPE_2 0x02000000      /* Addess Multiplexing Type 2 */
#define MAMR_AMA_TYPE_3 0x03000000      /* Addess Multiplexing Type 3 */
#define MAMR_AMA_TYPE_4 0x04000000      /* Addess Multiplexing Type 4 */
#define MAMR_AMA_TYPE_5 0x05000000      /* Addess Multiplexing Type 5 */
#define MAMR_DSA_MSK    0x00C00000      /* Disable Timer period mask */
#define MAMR_DSA_1_CYCL 0x00000000      /* 1 cycle Disable Period */
#define MAMR_DSA_2_CYCL 0x00400000      /* 2 cycle Disable Period */
#define MAMR_DSA_3_CYCL 0x00800000      /* 3 cycle Disable Period */
#define MAMR_DSA_4_CYCL 0x00C00000      /* 4 cycle Disable Period */
#define MAMR_G0CLA_MSK  0x00380000      /* General Line 0 Control A */
#define MAMR_G0CLA_A12  0x00000000      /* General Line 0 : A12 */
#define MAMR_G0CLA_A11  0x00080000      /* General Line 0 : A11 */
#define MAMR_G0CLA_A10  0x00100000      /* General Line 0 : A10 */
#define MAMR_G0CLA_A9   0x00180000      /* General Line 0 : A9 */
#define MAMR_G0CLA_A8   0x00200000      /* General Line 0 : A8 */
#define MAMR_G0CLA_A7   0x00280000      /* General Line 0 : A7 */
#define MAMR_G0CLA_A6   0x00300000      /* General Line 0 : A6 */
#define MAMR_G0CLA_A5   0x00380000      /* General Line 0 : A5 */
#define MAMR_GPL_A4DIS  0x00040000      /* GPL_A4 ouput line Disable */
#define MAMR_RLFA_MSK   0x0003C000      /* Read Loop Field A mask */
#define MAMR_RLFA_1X    0x00004000      /* The Read Loop is executed 1 time */
#define MAMR_RLFA_2X    0x00008000      /* The Read Loop is executed 2 times */
#define MAMR_RLFA_3X    0x0000C000      /* The Read Loop is executed 3 times */
#define MAMR_RLFA_4X    0x00010000      /* The Read Loop is executed 4 times */
#define MAMR_RLFA_5X    0x00014000      /* The Read Loop is executed 5 times */
#define MAMR_RLFA_6X    0x00018000      /* The Read Loop is executed 6 times */
#define MAMR_RLFA_7X    0x0001C000      /* The Read Loop is executed 7 times */
#define MAMR_RLFA_8X    0x00020000      /* The Read Loop is executed 8 times */
#define MAMR_RLFA_9X    0x00024000      /* The Read Loop is executed 9 times */
#define MAMR_RLFA_10X   0x00028000      /* The Read Loop is executed 10 times */
#define MAMR_RLFA_11X   0x0002C000      /* The Read Loop is executed 11 times */
#define MAMR_RLFA_12X   0x00030000      /* The Read Loop is executed 12 times */
#define MAMR_RLFA_13X   0x00034000      /* The Read Loop is executed 13 times */
#define MAMR_RLFA_14X   0x00038000      /* The Read Loop is executed 14 times */
#define MAMR_RLFA_15X   0x0003C000      /* The Read Loop is executed 15 times */
#define MAMR_RLFA_16X   0x00000000      /* The Read Loop is executed 16 times */
#define MAMR_WLFA_MSK   0x00003C00      /* Write Loop Field A mask */
#define MAMR_WLFA_1X    0x00000400      /* The Write Loop is executed 1 time */
#define MAMR_WLFA_2X    0x00000800      /* The Write Loop is executed 2 times */
#define MAMR_WLFA_3X    0x00000C00      /* The Write Loop is executed 3 times */
#define MAMR_WLFA_4X    0x00001000      /* The Write Loop is executed 4 times */
#define MAMR_WLFA_5X    0x00001400      /* The Write Loop is executed 5 times */
#define MAMR_WLFA_6X    0x00001800      /* The Write Loop is executed 6 times */
#define MAMR_WLFA_7X    0x00001C00      /* The Write Loop is executed 7 times */
#define MAMR_WLFA_8X    0x00002000      /* The Write Loop is executed 8 times */
#define MAMR_WLFA_9X    0x00002400      /* The Write Loop is executed 9 times */
#define MAMR_WLFA_10X   0x00002800      /* The Write Loop is executed 10 times*/
#define MAMR_WLFA_11X   0x00002C00      /* The Write Loop is executed 11 times*/
#define MAMR_WLFA_12X   0x00003000      /* The Write Loop is executed 12 times*/
#define MAMR_WLFA_13X   0x00003400      /* The Write Loop is executed 13 times*/
#define MAMR_WLFA_14X   0x00003800      /* The Write Loop is executed 14 times*/
#define MAMR_WLFA_15X   0x00003C00      /* The Write Loop is executed 15 times*/
#define MAMR_WLFA_16X   0x00000000      /* The Write Loop is executed 16 times*/
#define MAMR_TLFA_MSK   0x000003C0      /* Timer Loop Field A mask */
#define MAMR_TLFA_1X    0x00000040      /* The Timer Loop is executed 1 time */
#define MAMR_TLFA_2X    0x00000080      /* The Timer Loop is executed 2 times */
#define MAMR_TLFA_3X    0x000000C0      /* The Timer Loop is executed 3 times */
#define MAMR_TLFA_4X    0x00000100      /* The Timer Loop is executed 4 times */
#define MAMR_TLFA_5X    0x00000140      /* The Timer Loop is executed 5 times */
#define MAMR_TLFA_6X    0x00000180      /* The Timer Loop is executed 6 times */
#define MAMR_TLFA_7X    0x000001C0      /* The Timer Loop is executed 7 times */
#define MAMR_TLFA_8X    0x00000200      /* The Timer Loop is executed 8 times */
#define MAMR_TLFA_9X    0x00000240      /* The Timer Loop is executed 9 times */
#define MAMR_TLFA_10X   0x00000280      /* The Timer Loop is executed 10 times*/
#define MAMR_TLFA_11X   0x000002C0      /* The Timer Loop is executed 11 times*/
#define MAMR_TLFA_12X   0x00000300      /* The Timer Loop is executed 12 times*/
#define MAMR_TLFA_13X   0x00000340      /* The Timer Loop is executed 13 times*/
#define MAMR_TLFA_14X   0x00000380      /* The Timer Loop is executed 14 times*/
#define MAMR_TLFA_15X   0x000003C0      /* The Timer Loop is executed 15 times*/
#define MAMR_TLFA_16X   0x00000000      /* The Timer Loop is executed 16 times*/
#define MAMR_MAD_MSK    0x0000003F      /* Machine Address Mask */


/* Machine B Mode Register bit definition (MBMR - 0x10174) */

#define MBMR_BSEL       0x80000000      /* Bus select */
#define MBMR_RFEN       0x40000000      /* Refresh enable */
#define MBMR_OP_MSK     0x30000000      /* Command opcode mask */
#define MBMR_AMB_MSK    0x07000000      /* Addess Multiplexing size A */
#define MBMR_AMB_TYPE_0 0x00000000      /* Addess Multiplexing Type 0 */
#define MBMR_AMB_TYPE_1 0x01000000      /* Addess Multiplexing Type 1 */
#define MBMR_AMB_TYPE_2 0x02000000      /* Addess Multiplexing Type 2 */
#define MBMR_AMB_TYPE_3 0x03000000      /* Addess Multiplexing Type 3 */
#define MBMR_AMB_TYPE_4 0x04000000      /* Addess Multiplexing Type 4 */
#define MBMR_AMB_TYPE_5 0x05000000      /* Addess Multiplexing Type 5 */
#define MBMR_DSB_MSK    0x00C00000      /* Disable Timer period mask */
#define MBMR_DSB_1_CYCL 0x00000000      /* 1 cycle Disable Period */
#define MBMR_DSB_2_CYCL 0x00400000      /* 2 cycle Disable Period */
#define MBMR_DSB_3_CYCL 0x00800000      /* 3 cycle Disable Period */
#define MBMR_DSB_4_CYCL 0x00C00000      /* 4 cycle Disable Period */
#define MBMR_G0CLB_MSK  0x00380000      /* General Line 0 Control A */
#define MBMR_G0CLB_A12  0x00000000      /* General Line 0 : A12 */
#define MBMR_G0CLB_A11  0x00080000      /* General Line 0 : A11 */
#define MBMR_G0CLB_A10  0x00100000      /* General Line 0 : A10 */
#define MBMR_G0CLB_A9   0x00180000      /* General Line 0 : A9 */
#define MBMR_G0CLB_A8   0x00200000      /* General Line 0 : A8 */
#define MBMR_G0CLB_A7   0x00280000      /* General Line 0 : A7 */
#define MBMR_G0CLB_A6   0x00300000      /* General Line 0 : A6 */
#define MBMR_G0CLB_A5   0x00380000      /* General Line 0 : A5 */
#define MBMR_GPL_B4DIS  0x00040000      /* GPL_A4 ouput line Disable */
#define MBMR_RLFB_MSK   0x0003C000      /* Read Loop Field A mask */
#define MBMR_RLFB_1X    0x00004000      /* The Read Loop is executed 1 time */
#define MBMR_RLFB_2X    0x00008000      /* The Read Loop is executed 2 times */
#define MBMR_RLFB_3X    0x0000C000      /* The Read Loop is executed 3 times */
#define MBMR_RLFB_4X    0x00010000      /* The Read Loop is executed 4 times */
#define MBMR_RLFB_5X    0x00014000      /* The Read Loop is executed 5 times */
#define MBMR_RLFB_6X    0x00018000      /* The Read Loop is executed 6 times */
#define MBMR_RLFB_7X    0x0001C000      /* The Read Loop is executed 7 times */
#define MBMR_RLFB_8X    0x00020000      /* The Read Loop is executed 8 times */
#define MBMR_RLFB_9X    0x00024000      /* The Read Loop is executed 9 times */
#define MBMR_RLFB_10X   0x00028000      /* The Read Loop is executed 10 times */
#define MBMR_RLFB_11X   0x0002C000      /* The Read Loop is executed 11 times */
#define MBMR_RLFB_12X   0x00030000      /* The Read Loop is executed 12 times */
#define MBMR_RLFB_13X   0x00034000      /* The Read Loop is executed 13 times */
#define MBMR_RLFB_14X   0x00038000      /* The Read Loop is executed 14 times */
#define MBMR_RLFB_15X   0x0003C000      /* The Read Loop is executed 15 times */
#define MBMR_RLFB_16X   0x00000000      /* The Read Loop is executed 16 times */
#define MBMR_WLFB_MSK   0x00003C00      /* Write Loop Field A mask */
#define MBMR_WLFB_1X    0x00000400      /* The Write Loop is executed 1 time */
#define MBMR_WLFB_2X    0x00000800      /* The Write Loop is executed 2 times */
#define MBMR_WLFB_3X    0x00000C00      /* The Write Loop is executed 3 times */
#define MBMR_WLFB_4X    0x00001000      /* The Write Loop is executed 4 times */
#define MBMR_WLFB_5X    0x00001400      /* The Write Loop is executed 5 times */
#define MBMR_WLFB_6X    0x00001800      /* The Write Loop is executed 6 times */
#define MBMR_WLFB_7X    0x00001C00      /* The Write Loop is executed 7 times */
#define MBMR_WLFB_8X    0x00002000      /* The Write Loop is executed 8 times */
#define MBMR_WLFB_9X    0x00002400      /* The Write Loop is executed 9 times */
#define MBMR_WLFB_10X   0x00002800      /* The Write Loop is executed 10 times*/
#define MBMR_WLFB_11X   0x00002C00      /* The Write Loop is executed 11 times*/
#define MBMR_WLFB_12X   0x00003000      /* The Write Loop is executed 12 times*/
#define MBMR_WLFB_13X   0x00003400      /* The Write Loop is executed 13 times*/
#define MBMR_WLFB_14X   0x00003800      /* The Write Loop is executed 14 times*/
#define MBMR_WLFB_15X   0x00003C00      /* The Write Loop is executed 15 times*/
#define MBMR_WLFB_16X   0x00000000      /* The Write Loop is executed 16 times*/
#define MBMR_TLFB_MSK   0x000003C0      /* Timer Loop Field A mask */
#define MBMR_TLFB_1X    0x00000040      /* The Timer Loop is executed 1 time */
#define MBMR_TLFB_2X    0x00000080      /* The Timer Loop is executed 2 times */
#define MBMR_TLFB_3X    0x000000C0      /* The Timer Loop is executed 3 times */
#define MBMR_TLFB_4X    0x00000100      /* The Timer Loop is executed 4 times */
#define MBMR_TLFB_5X    0x00000140      /* The Timer Loop is executed 5 times */
#define MBMR_TLFB_6X    0x00000180      /* The Timer Loop is executed 6 times */
#define MBMR_TLFB_7X    0x000001C0      /* The Timer Loop is executed 7 times */
#define MBMR_TLFB_8X    0x00000200      /* The Timer Loop is executed 8 times */
#define MBMR_TLFB_9X    0x00000240      /* The Timer Loop is executed 9 times */
#define MBMR_TLFB_10X   0x00000280      /* The Timer Loop is executed 10 times*/
#define MBMR_TLFB_11X   0x000002C0      /* The Timer Loop is executed 11 times*/
#define MBMR_TLFB_12X   0x00000300      /* The Timer Loop is executed 12 times*/
#define MBMR_TLFB_13X   0x00000340      /* The Timer Loop is executed 13 times*/
#define MBMR_TLFB_14X   0x00000380      /* The Timer Loop is executed 14 times*/
#define MBMR_TLFB_15X   0x000003C0      /* The Timer Loop is executed 15 times*/
#define MBMR_TLFB_16X   0x00000000      /* The Timer Loop is executed 16 times*/
#define MBMR_MAD_MSK    0x0000003F      /* Machine Address Mask */


/* Machine C Mode Register bit definition (MCMR - 0x10178) */

#define MCMR_BSEL       0x80000000      /* Bus select */
#define MCMR_RFEN       0x40000000      /* Refresh enable */
#define MCMR_OP_MSK     0x30000000      /* Command opcode mask */
#define MCMR_AMC_MSK    0x07000000      /* Addess Multiplexing size A */
#define MCMR_AMC_TYPE_0 0x00000000      /* Addess Multiplexing Type 0 */
#define MCMR_AMC_TYPE_1 0x01000000      /* Addess Multiplexing Type 1 */
#define MCMR_AMC_TYPE_2 0x02000000      /* Addess Multiplexing Type 2 */
#define MCMR_AMC_TYPE_3 0x03000000      /* Addess Multiplexing Type 3 */
#define MCMR_AMC_TYPE_4 0x04000000      /* Addess Multiplexing Type 4 */
#define MCMR_AMC_TYPE_5 0x05000000      /* Addess Multiplexing Type 5 */
#define MCMR_DSC_MSK    0x00C00000      /* Disable Timer period mask */
#define MCMR_DSC_1_CYCL 0x00000000      /* 1 cycle Disable Period */
#define MCMR_DSC_2_CYCL 0x00400000      /* 2 cycle Disable Period */
#define MCMR_DSC_3_CYCL 0x00800000      /* 3 cycle Disable Period */
#define MCMR_DSC_4_CYCL 0x00C00000      /* 4 cycle Disable Period */
#define MCMR_G0CLC_MSK  0x00380000      /* General Line 0 Control A */
#define MCMR_G0CLC_A12  0x00000000      /* General Line 0 : A12 */
#define MCMR_G0CLC_A11  0x00080000      /* General Line 0 : A11 */
#define MCMR_G0CLC_A10  0x00100000      /* General Line 0 : A10 */
#define MCMR_G0CLC_A9   0x00180000      /* General Line 0 : A9 */
#define MCMR_G0CLC_A8   0x00200000      /* General Line 0 : A8 */
#define MCMR_G0CLC_A7   0x00280000      /* General Line 0 : A7 */
#define MCMR_G0CLC_A6   0x00300000      /* General Line 0 : A6 */
#define MCMR_G0CLC_A5   0x00380000      /* General Line 0 : A5 */
#define MCMR_GPL_C4DIS  0x00040000      /* GPL_A4 ouput line Disable */
#define MCMR_RLFC_MSK   0x0003C000      /* Read Loop Field A mask */
#define MCMR_RLFC_1X    0x00004000      /* The Read Loop is executed 1 time */
#define MCMR_RLFC_2X    0x00008000      /* The Read Loop is executed 2 times */
#define MCMR_RLFC_3X    0x0000C000      /* The Read Loop is executed 3 times */
#define MCMR_RLFC_4X    0x00010000      /* The Read Loop is executed 4 times */
#define MCMR_RLFC_5X    0x00014000      /* The Read Loop is executed 5 times */
#define MCMR_RLFC_6X    0x00018000      /* The Read Loop is executed 6 times */
#define MCMR_RLFC_7X    0x0001C000      /* The Read Loop is executed 7 times */
#define MCMR_RLFC_8X    0x00020000      /* The Read Loop is executed 8 times */
#define MCMR_RLFC_9X    0x00024000      /* The Read Loop is executed 9 times */
#define MCMR_RLFC_10X   0x00028000      /* The Read Loop is executed 10 times */
#define MCMR_RLFC_11X   0x0002C000      /* The Read Loop is executed 11 times */
#define MCMR_RLFC_12X   0x00030000      /* The Read Loop is executed 12 times */
#define MCMR_RLFC_13X   0x00034000      /* The Read Loop is executed 13 times */
#define MCMR_RLFC_14X   0x00038000      /* The Read Loop is executed 14 times */
#define MCMR_RLFC_15X   0x0003C000      /* The Read Loop is executed 15 times */
#define MCMR_RLFC_16X   0x00000000      /* The Read Loop is executed 16 times */
#define MCMR_WLFC_MSK   0x00003C00      /* Write Loop Field A mask */
#define MCMR_WLFC_1X    0x00000400      /* The Write Loop is executed 1 time */
#define MCMR_WLFC_2X    0x00000800      /* The Write Loop is executed 2 times */
#define MCMR_WLFC_3X    0x00000C00      /* The Write Loop is executed 3 times */
#define MCMR_WLFC_4X    0x00001000      /* The Write Loop is executed 4 times */
#define MCMR_WLFC_5X    0x00001400      /* The Write Loop is executed 5 times */
#define MCMR_WLFC_6X    0x00001800      /* The Write Loop is executed 6 times */
#define MCMR_WLFC_7X    0x00001C00      /* The Write Loop is executed 7 times */
#define MCMR_WLFC_8X    0x00002000      /* The Write Loop is executed 8 times */
#define MCMR_WLFC_9X    0x00002400      /* The Write Loop is executed 9 times */
#define MCMR_WLFC_10X   0x00002800      /* The Write Loop is executed 10 times*/
#define MCMR_WLFC_11X   0x00002C00      /* The Write Loop is executed 11 times*/
#define MCMR_WLFC_12X   0x00003000      /* The Write Loop is executed 12 times*/
#define MCMR_WLFC_13X   0x00003400      /* The Write Loop is executed 13 times*/
#define MCMR_WLFC_14X   0x00003800      /* The Write Loop is executed 14 times*/
#define MCMR_WLFC_15X   0x00003C00      /* The Write Loop is executed 15 times*/
#define MCMR_WLFC_16X   0x00000000      /* The Write Loop is executed 16 times*/
#define MCMR_TLFC_MSK   0x000003C0      /* Timer Loop Field A mask */
#define MCMR_TLFC_1X    0x00000040      /* The Timer Loop is executed 1 time */
#define MCMR_TLFC_2X    0x00000080      /* The Timer Loop is executed 2 times */
#define MCMR_TLFC_3X    0x000000C0      /* The Timer Loop is executed 3 times */
#define MCMR_TLFC_4X    0x00000100      /* The Timer Loop is executed 4 times */
#define MCMR_TLFC_5X    0x00000140      /* The Timer Loop is executed 5 times */
#define MCMR_TLFC_6X    0x00000180      /* The Timer Loop is executed 6 times */
#define MCMR_TLFC_7X    0x000001C0      /* The Timer Loop is executed 7 times */
#define MCMR_TLFC_8X    0x00000200      /* The Timer Loop is executed 8 times */
#define MCMR_TLFC_9X    0x00000240      /* The Timer Loop is executed 9 times */
#define MCMR_TLFC_10X   0x00000280      /* The Timer Loop is executed 10 times*/
#define MCMR_TLFC_11X   0x000002C0      /* The Timer Loop is executed 11 times*/
#define MCMR_TLFC_12X   0x00000300      /* The Timer Loop is executed 12 times*/
#define MCMR_TLFC_13X   0x00000340      /* The Timer Loop is executed 13 times*/
#define MCMR_TLFC_14X   0x00000380      /* The Timer Loop is executed 14 times*/
#define MCMR_TLFC_15X   0x000003C0      /* The Timer Loop is executed 15 times*/
#define MCMR_TLFC_16X   0x00000000      /* The Timer Loop is executed 16 times*/
#define MCMR_MAD_MSK    0x0000003F      /* Machine Address Mask */


/* PIT Status and Control Register bit definition (PISCR - 0x10240) */

#define PISCR_PS	0x0080		/* Periodic interrupt Status */
#define PISCR_PIE	0x0004		/* Periodic Interrupt Enable */
#define PISCR_PTF 	0x0002		/* Periodic Interrupt Frequency */
#define PISCR_PTE	0x0001		/* Periodic Timer Enable */

/* System Clock Control Register bit definition (SCCR - 0x10C82) */

#define SCCR_CLPD      	0x00000004	/* CPM low power disable */
#define SCCR_DFBRG_MSK 	0x00000003	/* Div. factor of BRGCLK from VCO_OUT*/

#ifdef  __cplusplus
}
#endif

#endif /* __INCsbcm8260Siuh */
